#Private cache software software
#Private cache software code

The horizontal axis represents time, the vertical axis corresponds to memory locations, and each point is a core access.

#Private cache software code

Examples include fetching program code in a linear sequential manner and when the core accesses member i in an array, it increases the likelihood it will also access member i+1.įigure 2 below shows an example of a well localized access pattern generated by a core. Spatial locality, which assumes that if the core accesses a memory location, it will access nearby memory locations as well in the near future. Examples include code implementing loops for which the same lines of code are read again and again by the core and when the core accesses stack memory repeatedly when calling and returning from functions. Temporal locality, which assumes that if the core accesses a memory location, it will do so again in the near future. When defining locality, we distinguish between two types of localities: This can be avoided by cache partitioning, as explained later in this article.Ĭache memory topologies use the assumption that the core accesses the memory system locally. * Conflict miss : A memory location was in the cache at some point in time, but was thrashed (replaced by the content of another memory location) before the current core access, due to one of two reasons: 1) insufficient associativity, which is less frequent in architectures such as the SC3850 core subsystem, which has 8 way caches, and 2) replacement mechanism made imperfect choices. * Capacity miss : A memory location was in the cache at some point in time, but was thrashed by another memory location (before the current core access), due to the finite size of the cache. * Compulsory miss : The first core access to a memory location that was never in the cache (we'll explain how even these “compulsory” misses can be avoided). There are three main types of cache misses: To minimize core wait state, both the number of misses and the average miss penalty should be minimized. The core waits for the fetch to be processed.

The result of a cache miss is an automatic fetch from higher memory (next level of cache or main memory). * Miss : The core accesses a memory location for which the content is not in the cache. In this case, the access is serviced directly by the cache without any penalties. * Hit : The core accesses a memory location for which the content is already in the cache. This article uses the following definitions:

#Private cache software software

Therefore, the software must know when the data is allocated and it must be aware that the same address in the near memory has different contents. The programmer must configure the DMA to move data from a far memory to a near memory. In comparison, a DMA-based system uses a near memory with its own fixed addresses (memory locations). If the content from a memory location that the core needs is not in the cache, the cache automatically fetches it from the main memory. The core accesses the cached copies by their original memory locations (rr by their virtual address, in case translation is used), which means that the core can conveniently view a static memory map. Additional memories are larger, slower and may reside on chip like shared on chip M3 or off chip like off chip DDR.įigure 1: Typical Modern DSP Memory Hierarchy The larger, second level of memory can be cache (L2) or a regular SRAM memory (M2). Įach DSP core has its private L1 caches, normally separated to Instruction and Data. A typical memory hierarchy of a modern DSP is shown in Figure 1 below. A cache-based system uses small, fast memories to store short term copies of data stored in the slower main memory.